Meaning
Hardware delay occurs when an atomic instruction forces a processor to assert a lock signal on the system bus, preventing other execution units from accessing shared memory. Multi-processor platforms experience this bus lock latency when cache line splits force physical locking of the memory bus rather than local cache resolution. This action blocks all core transactions to ensure atomic read-modify-write safety.
Performance Degradation
Execution pipelines stall while the hardware waits for the memory controller to release the locked bus. Real-time threads suffer severe execution delays when execution reliance is based on predictable sub-microsecond response times. Unaligned atomic operations generate the most severe throughput losses.
System Mechanism
Shared-memory architectures use cache coherency protocols to manage atomic operations within a single cache line without asserting a physical bus lock. However, when a memory transaction crosses a cache line boundary, a split lock is triggered, which forces the processor to invoke a hardware bus lock. The lock remains active until the transaction completes, halting all peripheral and core traffic.
Software that relies on atomic operations must avoid these misaligned memory boundaries to maintain system throughput.
Detection Method
Performance monitoring counters log the occurrence of split locks to help trace latency spikes. Modern operating systems can configure the kernel to block or rate-limit processes that trigger split locks. Proper compiler alignment of data structures prevents the physical lock from ever occurring.
